Oregon State University

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PhD Final Oral Examination – Allen Waters


Thursday, March 5, 2015 3:00 PM - 5:00 PM

Automated Verilog-to-Layout Synthesis of ADCs Using Custom Analog Cells
A procedure for automating the design and layout of analog-to-digital converters (ADCs) is presented. This procedure makes use of the existing synthesis and place-and-route tools that are common in digital circuit design. A method for adding rudimentary analog cells to the standard library is described, allowing the designer to synthesize mixed-signal designs from Verilog code. By using cells that are simple and highly scalable, the same Verilog code may be used to implement the design in any number of process nodes, for rapid portability and scalability. Two different ADC architectures are implemented as proofs of concept: first, a third-order MASH ADC is fabricated in 130nm and 65nm CMOS, taking advantage of the structure's tolerance to the mismatch introduced by the automated place-and-routing. Second, a Nyquist-rate pipeline ADC using the highly-scalable ring amplifier is fabricated in 65nm CMOS. The measurement results from these chips show that synthesized ADCs can achieve moderate performance with drastically reduced design time compared to manual layout.

Major Advisor: Un-Ku Moon
Committee: Karti Mayaram
Committee: Gabor Temes
Committee: Huaping Liu
GCR: Karen Shell


Kelley Engineering Center (campus map)
1005
Nicole Thompson
1 541 737 3617
Nicole.Thompson at oregonstate.edu
Sch Elect Engr/Comp Sci
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