Oregon State University

Can’t find an event? We’re busy migrating to a new event calendar. Try looking new calendar



Event Details

MS Final Examination – Wojtek Rajski

Wednesday, March 9, 2016 4:00 PM - 6:00 PM

Many Parallel Fault Simulation
The number of transistors on an integrated circuit doubling every 18 to 24 months means that the complexity of testing these circuits grows exponentially. With this growth there is a continuing need for newer and faster ways to test these circuits. In this report I introduce a novel fault simulator based on Parallel Pattern Single Fault Propagation (PPSFP). Historically PPSFP has been implemented using gate-levelized netlists. This is not optimal because it does not take advantage of spatial and temporal locality in modern superscalar processors. In this report we show that by merging the methodology of PPSFP to that of superscalar processors, we can dramatically increase performance. This is done by tiling based on the structure of dependencies between Fanout Free Regions (FFRs). By tiling in this fashion, we can propagate multiple faults and perform backward tracing simultaneously. Furthermore we leverage Single Instruction Multiple Date (SIMD) operations by compactly fitting FFRs into both cache coalesced and vector aligned data structures. This has the added effect of streamlining data access which results in more performance benefits. With these optimizations, further analysis was done with these data structures on real industrial designs which led to improvements of parallelization. Most notably in my research I have found how uneven the workload distribution between FFRs can be and show multiple ways of combating this issue.

Major Advisor: Mike Bailey
Committee: Kevin McGrath
Committee: Jennifer Parham-Mocello

Kelley Engineering Center (campus map)
Nicole Thompson
1 541 737 3617
Nicole.Thompson at oregonstate.edu
Sch Elect Engr/Comp Sci
This event appears on the following calendars: