Oregon State University

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Event Details

PhD Oral Preliminary Examination – Abhishek Agrawal

Monday, May 9, 2016 10:00 AM - 12:00 PM

A Scalable 28GHz Coupled-PLL in 65nm CMOS with Single-Wire Synchronization for Large-Scale 5G mm-Wave Arrays
This research presents a scalable, single-wire synchronization architecture and circuits for mm-Wave arrays that preserve the simplicity of daisy-chained LO distribution, compensate for phase offset due to interconnect, and provide phase noise improvement with an increase number of PLLs. Measurements on a scalable 28GHz prototype demonstrate a 21% improvement in rms jitter and 3.4dB improvement in phase noise at a 10MHz offset when coupling 28GHz PLLs across three different ICs.

Major Advisor: Arun Natarajan
Committee: Un-Ku Moon
Committee: Karti Mayaram
Committee: Andreas Weisshaar
GCR: William Hetherington

Kelley Engineering Center (campus map)
Nicole Thompson
1 541 737 3617
Nicole.Thompson at oregonstate.edu
Sch Elect Engr/Comp Sci
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