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PhD Oral Preliminary Examination – Mahmoud Sadollahi


Wednesday, December 7, 2016 2:00 PM - 4:00 PM

Power Efficient Architectures for Medium-high Resolution Analog-to-Digital Converters
Analog-to-digital converters are essential blocks of the portable devices that we are using today. Wireless sensors, body implanted devices, communication devices and so forth requires low power ADCs. Therefore achieving higher resolution and bandwidth with lower power consumption is targeted in ADCs design. In these work power efficient ADCs for medium-high resolution is presented.

First an ultra-low power successive approximation register SAR ADC is presented. The ADC is an 11-bit single-ended, low power, area efficient with small loading effect targeted for biomedical applications. The design features an energy-efficient switching technique to cover an input range twice the reference voltage. The ADC’s loading effect to previous stage reduced by using single-ended structure and eliminating the largest capacitor in switching network. All building blocks were designed in subthreshold for power efficiency, with asynchronous self-controlled SAR logic. The ADC was fabricated in 0.18 µm CMOS 2P4M process. The measured peak SNDR was 60.5 dB, the SFDR was 72 dB, the DNL +0.6/-0.37 LSB and the INL +0.94/-0.89 LSB. The total power consumption was 250 nW from 0.75V supply voltage. This gives Walden FoM of 28.8 fJ/Conv-step.

In addition, a noise-coupled VCO-based quantizer is presented, and based on that a single-loop two stage delta-sigma ADC with 3rd order of noise-shaping with only one active integrator is presented. By applying the noise-coupling technique a second order noise-shaped quantizer achieved, which gets one from VCO-quantizer and another one from noise-coupling technique. This quantizer is used in a single-loop two stage ∆Σ ADC where the active integrator only handles the quantization noise. Therefore the OTA requirements for integrator is very relaxed by applied technique. Input to the VCO quantizer is a quantization noise which is in linear range of the VCO. A design example with sampling frequency of 160 MHz is described in this work.

Major Advisor: Gabor Temes
Committee: Kartikeya Mayaram
Committee: Huaping Liu
Committee: Matthew Johnston
GCR: William Warnes


Kelley Engineering Center (campus map)
1126
Nicole Thompson
1 541 737 3617
Nicole.Thompson at oregonstate.edu
Sch Elect Engr/Comp Sci
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