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PhD Oral Preliminary Examination – Jason Muhlestein


Wednesday, December 7, 2016 8:00 AM - 10:00 AM

Power Efficient Analog-to-Digital Converters Using Hybrid Voltage and Time Domain Quantization
The internet-of-things is a growing market segment which is based on an array of portable communication devices with high power efficiency. Advanced semiconductor technology can easily improve their digital performance, but the same cannot be said for the analog blocks which are vital to their operation. High performance analog circuits continue to use conventional techniques at the expense of power efficiency. Deeply scaled CMOS exaggerates this trade-off, opening the door for novel system techniques which take advantage of the digital nature of sub-micron transistors.

This research focuses on a highly digital ADC which mitigates the short channel effects of limited output swing and low intrinsic gain, while also benefiting from process scaling. The proposed multi-domain ADC performs quantization on both voltage and time domain signals to relax the power-performance trade-off, leading to a high resolution, high efficiency data converter. A prototype ADC was fabricated in 180nm CMOS, showing an SNDR of 73 dB, operating at 20 MHz sampling frequency, with a power consumption of 1.28 mW.

Major Advisor: Un-Ku Moon
Committee: Kartikeya Mayaram
Committee: Arun Natarajan
Committee: Gabor Temes
GCR: Leonard Coop


Kelley Engineering Center (campus map)
1007
Nicole Thompson
1 541 737 3617
Nicole.Thompson at oregonstate.edu
Sch Elect Engr/Comp Sci
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