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MS Final Examination – Lakshman Madhav Kollipara


Thursday, December 8, 2016 9:00 AM - 11:00 AM

Design of High-Performance NoCs for GPGPUs
General Purpose Graphics Processing Units (GPGPUs) are used in modern computational workloads for their thread level parallelism (TLP) and highly programmable cores which allow thousands of threads to execute in Parallel.

The fast-scaling of GPGPUs have increased the demand for performance optimizations on Network-On-Chip (NoC) designs. NoCs should minimize the blocking efficiency by limiting the usage of virtual channels (VCs) and physical links while avoiding deadlocks. Previous works have exploited NoC designs in the Chip Multiprocessor (CMP) environments but not in GPGPU systems. Unlike CMPs, traffic is highly asymmetric in the GPGPUs because of Many cores and only few Memory Controllers (MCs).

The highly asymmetric traffic impacts the resource utilization and performance of NoC. This project aims at analyzing the communication demands in GPGPUs, efficient MC placements, different VC allocations and routing patterns on a single network NoC.

The existing work has introduced the concept of VC monopolization which increases the performance but also increases the link contention and power consumption. With this project, we further optimized the VC monopolization scheme by reducing the link contention resulting in higher performance and reduced power consumption. The proposed schemes improve performance of IPC by 90% and Latency by 132% compared to baseline versions.

Major Advisor: Lizhong Chen
Committee: Bechir Hamdaoui
Committee: Anita Sarma


Kelley Engineering Center (campus map)
4107
Nicole Thompson
1 541 737 3617
Nicole.Thompson at oregonstate.edu
Sch Elect Engr/Comp Sci
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