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MS Final Examination – Hui Zhang


Thursday, December 7, 2017 1:30 PM - 3:30 PM

Hybrid Analog to Digital Converter Architecture for Sensor Network Applications
Analog to digital converters (ADCs) are the key building block for sensor applications, such as wireless communications and digital electronics. These applications require ADCs to have medium to high accuracy (normally from 10-14 bits) and relatively low signal bandwidth (ranging from 100Hz-150kHz). Since those applications are often powered by batteries, high power efficiency of the ADCs is one of the biggest challenge of the design. Recently, SAR ADCs have been used inside of a delta-sigma modulator to achieve relatively high resolution while maintaining excellent power efficiency. However, the passive noise shaping from the SAR ADC can cause low frequency quantization noise leakage, which degrades the overall accuracy. Besides, the maximum noise-shaping order has been limited to second-order in reported works. To achieve a higher order NTF and reduce the inband quantization noise leakage, a single opamp-based third-order delta-sigma modulator with noise-shaping SAR quantizer is proposed in this work. Designed with 65nm CMOS technology, the prototype modulator attains 84.5dB SNDR over 50kHz signal bandwidth sampled at 3.2MHz in simulation. The power consumption of the ADC is 50.7µW.

Major Advisor: Terri Fiez
Co-Major Advisor: Karti Mayaram
Committee: Un-Ku Moon
GCR: Jimmy Yang


Kelley Engineering Center (campus map)
1005
Calvin Hughes
1 541 737 3168
Calvin.Hughes at oregonstate.edu
Sch Elect Engr/Comp Sci
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