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PhD Oral Preliminary Examination – Tao Wang


Monday, October 3, 2011 3:30 PM - 5:30 PM

A Low-Power 18-bit Delta-Sigma ADC Employing Direct-Charge-Transfer Adder for Sensor Applications
A 1.1-mW 18-bit resolution 20-kHz bandwidth low-power high-resolution delta-sigma instrumentation ADC is being designed. The simulated Figure-of-Merit (FoM) is 0.37pJ/conv., which is among the best in very high resolution (≥16 bits) audio bandwidth range instrumentation ADC applications. The Over-sampling-ratio (OSR) is 64. A third-order equivalent 3.9-bit modulator loop is employed to get enough quantization noise suppression. To reduce power dissipation, two new techniques are proposed. Direct-Charge-Transfer (DCT) adder greatly saves power by keeping the adder feedback factor unity. However, the inherent delay introduced by DCT adder will cause instability and complex additional branches are needed for compensation. A simple and economic way is proposed to absorb the delay from the DCT adder. A modified power efficient noise-shaping enhancement technique is also proposed which feeds differentiated quantization noise to the input of the second integrator, saving power by using less active components. The analog/digital power supply is 5V/1.8V and full scale is 3V. The core area is 0.4 mm².

 Major Advisor: Gabor Temes
Committee: Pavan Hanumolu, Huaping Liu, John Conley, Jr.
GCR: Kagan Tumer


Kelley Engineering Center (campus map)
1114
Shannon Thompson
1 541 737 7234
shannon.thompson at oregonstate.edu
Sch Elect Engr/Comp Sci
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