Oregon State University

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MS Final Oral Examination – Tushar Uttarwar


Monday, November 21, 2011 3:00 PM - 5:00 PM

Digital Multiplying Delay Locked Loop for High Frequency Clock Generation
As Moore’s Law continues to give rise to ever shrinking channel lengths, circuits are becoming more digital and ever increasingly faster. Generating high frequency clocks in such scaled processes is becoming a tough challenge. Digital phase locked loops (DPLLs) are being explored as an alternative to conventional analog PLLs but suffer from issues such as low bandwidth and higher quantization noise. A digital multiplying delay locked loop (DMDLL) is proposed which aims at leveraging the benefit of high bandwidth of DLL while at the same time achieving the frequency multiplication property of PLL. It also offers the benefits of easier portability across process and occupies lesser area.

The proposed DMDLL uses a simple flip-flop as 1-bit TDC (Time Digital Converter) for Phase Detector (PD). A digital accumulator acts as integrator for loop filter while a Δ-Σ DAC in combination with a VCO acts like a DCO. A carefully designed select logic in conjunction with a MUX achieves frequency multiplication. The proposed digital MDLL is taped out in 130nm process and tested to obtain 1.4GHz output frequency with 1.6ps RMS jitter, 17ps pk-pk jitter and -50dbC/Hz reference spurs.

Major Advisor: Pavan Hanumolu
Committee: Un-Ku Moon
Committee: Gabor Temes
GCR: John Parmigiani

 


Kelley Engineering Center (campus map)
1114
Ferne Simendinger
1 541 737 3617
ferne.simendinger at oregonstate.edu
Sch Elect Engr/Comp Sci
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