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PhD Final Oral Examination - Rajesh Inti


Monday, November 28, 2011 2:00 PM - 4:00 PM

Highly Digital Power Efficient Techniques for Serial Links
Low power, high speed serial transceivers are employed in a wide range of applications ranging from chip-to-chip, backplane, and optical interconnects. Apart from being capable of handling a wide range of data rates, the transceivers should have low power consumption (mW/Gb/s) and be fully integrated. This work discusses enabling techniques to implement such transceivers. Specifically, three designs: (1) a 0.5-4 Gb/s serial link which uses current recycling to reduce power dissipation and (2) a 0.5-2.5 Gb/s reference-less clock and data recovery circuit which uses a novel frequency detector to achieve unlimited acquisition range and (3) a 2-4 Gb/s low power receiver architecture capable of resolving multiple signalling formats with a simplified XOR based phase rotating PLL will be presented.  All the three circuit topologies are highly digital and aim to address the requirements of wide operating range, low power dissipation while being fully integrated. Measured results obtained from the prototypes illustrate the effectiveness of the proposed design techniques.

Major Advisor: Pavan Hanumolu
Committee: Un-Ku Moon
Committee: Karti Mayaram
Committee: Gabor Temes
GCR: William Warnes 


Kelley Engineering Center (campus map)
1007
Ferne Simendinger
1 541 737 2889
ferne at eecs.oregonstate.edu
Sch Elect Engr/Comp Sci
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