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PhD Final Oral Examination - Ho-Young Lee


Wednesday, November 30, 2011 11:30 AM - 1:30 PM

Power-efficient Nyquist ADC Design Techniques
This thesis presents two different approaches to achieving high power-efficiency from a two-step pipelined architecture, which is generally known as one of the most power-consuming analog-to-digital converters.

In the first approach, an analog feedback loop of a residue amplifier in a two-step pipelined analog-to-digital converter is reconfigured digitally using a single comparator and an R-2R digital-to-analog converter. This comparator-based structure can reduce power consumption of a conventional two-step pipelined analog-to-digital converter which consists of an opamp-based residue amplifier followed by a second stage analog-to-digital converter. A 10-b prototype analog-to-digital converter achieves an FOM of 121 fJ/conversion-step under 0.7-V supply.

The second approach provides a way to achieve low power consumption for a high-resolution two-step pipelined analog-to-digital converter. An opamp is designed to consume optimized static power using a quarter-scaled residue gain together with minimized loading capacitance from the proposed second stage. A 14-b prototype analog-to-digital converter achieves an FOM of 31.3 fJ/conversion-step with 11.4-b ENOB, which is the lowest FOM in high-resolution analog-to-digital converters having greater than 10-b ENOB.

Finally, the potential for further power reduction in a two-step pipelined analog-to-digital converter is discussed as a topic for future research.

Major Advisor: Un-Ku Moon
Committee: Gabor Temes
Committee: Karti Mayaram
Committee: Pavan Hanumolu
GCR: David Hackleman


Kelley Engineering Center (campus map)
1007
Ferne Simendinger
1 541 737 2889
ferne at eecs.oregonstate.edu
Sch Elect Engr/Comp Sci
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