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Event Details

PhD Oral Preliminary Examination - Tao Jiang

Wednesday, November 30, 2011 2:00 PM - 4:00 PM

Design techniques for ultra-high-speed, medium-resolution, low-power analog-to-digital converters
Ultra-high-speed (>10 GS/s), medium-resolution (5~6 bit), low-power (<50 mW) analog-to-digital converter finds it application in the areas like digital oscilloscopes, next-generation serial link receivers, and optical circuits. There are three big challenges to make a successful design, however. First, time-interleaving architecture has to be employed in order to achieve over 10 GS/s sampling rate, with the trade-off of the number of channels and the sampling rate in each channel. Phase misalignment and channel mismatch must also be considered. Second, timing accuracy, especially dynamic jitter of sampling clock becomes a major concern at ultra high frequency, and certain techniques must be take to address it. Finally, to achieve low power consumption, Flash architecture is not suitable to serve as the sub-ADC, and a low-power sub-ADC that can work at relatively high speed need to be designed.

A single-channel 1.25-GS/s, 6-bit, loop-unrolled asynchronous SAR ADC has already been designed in 40nm CMOS as the protype of the required sub-ADC. Based on that previous work, a 12-GS/s 6-b 50-mW ADC is also designed in 40nm CMOS, with 8 time-interleaved channels of sub-ADC of Flash-SAR hybrid structure, each running at 1.5 GS/s. A modified bootstrapping switch is used in the track-and-hold circuit, introducing a global clock signal to synchronize the cut-off instants of each different channel, therefore improve the phase alignment and reduce distortion. The global clock is provided by a CML buffer which is injected by off-chip low-noise sine-wave signal, so that the RMS dynamic jitter is low for better ENOB performance.

Major Advisor: Patrick Chiang
Committee: Gabor Temes
Committee: Huaping Liu
Committee: Albrecht Jander
GCR: Abdollah Farsoni

Kelley Engineering Center (campus map)
Ferne Simendinger
1 541 737 2889
ferne at eecs.oregonstate.edu
Sch Elect Engr/Comp Sci
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