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PhD Oral Preliminary Examination – Jon Guerber


Thursday, February 2, 2012 1:00 PM - 3:00 PM

Time and Statistical Information Utilization in SAR ADCs
In an industrial and consumer electronic marketplace that is increasingly demanding greater real-world interactivity in portable and distributed devices, analog to digital converter efficiency and performance is being carefully examined. One architecture, the successive approximation (SAR) analog to digital converter (ADC), has become popular for its high efficiency at mid-speed and resolution requirements. This is due to the one core single bit quantizer, lack of residue amplification, and large digital domain processing allowing for easy process scaling.

This work examines the traditional binary capacitive SAR ADC time and statistical information and proposes new structures that optimize ADC performance. The Ternary SAR (TSAR) uses the quantizer delay information to enhance accuracy, speed and power consumption of the overall SAR while providing multi-level redundancy. The early reset merged capacitor switching SAR (EMCS) identifies lost information in the SAR subtraction and optimizes a full binary quanitzer structure for a Ternary MCS DAC. Residue Shaping is demonstrated in SAR and pipeline configurations to allow for an extra bit of signal to noise quantization ratio (SQNR) due to multi-level redundancy.

Finally, the feedback initialized ternary SAR (FITSAR) is proposed which splits a TSAR into separate binary and ternary sub-ADC structures for speed and power benefits with an inter-stage encoding that not only maintains residue shaping across the binary SAR, but allows for a nearly optimally minimal energy consumption for capacitive ternary DACs.

Major Advisor:  Un-Ku Moon
Committee: Pavan Hanumolu, Gabor Temes, Huaping Liu
GCR: Brady Gibbons


Kelley Engineering Center (campus map)
1114
Shannon Thompson
1 541 737 7234
shannon.thompson at oregonstate.edu
Sch Elect Engr/Comp Sci
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