Oregon State University

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Event Details

PhD Final Oral Examination – Sang Hyeon Lee

Tuesday, May 29, 2012 12:00 PM - 2:00 PM

Novel structures for high-speed, low-power delta-sigma data converters
A cascade switched-capacitor ΔΣ analog-to-digital converter, suitable for WLANs, is presented. It uses a doublesampling scheme with single set of DAC capacitors, and an improved low-distortion architecture with an embedded-adder integrator. The proposed architecture eliminates one active stage, and reduces the output swings in the loop-filter and hence the non-linearity. It was fabricated with a 0.18um CMOS process.

The prototype chip achieves 75.5 dB DR, 74 dB SNR, 73.8 dB SNDR, -88.1 dB THD, and 90.2 dB SFDR over a 10 MHz signal band with an FoM of 0.27 pJ/conv-step.

Major Advisor: Gabor Temes
Committee: Pavan Hanumolu
Committee: Thinh Nguyen
Committee: Raviv Raich
GCR: William Warnes

Kelley Engineering Center (campus map)
Shannon Thompson
1 541 737 7234
shannon.thompson at oregonstate.edu
Sch Elect Engr/Comp Sci
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