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PhD Final Oral Examination – Tao Wang


Tuesday, May 29, 2012 2:00 PM - 4:00 PM

Low-Power High-Resolution Delta-Sigma ADC Design Techniques
This dissertation presents a low-power high-resolution delta-sigma ADC. Two new architectural design techniques are proposed to reduce the power dissipation of the ADC. Compared to the conventional active adder, the direct charge transfer (DCT) adder greatly saves power. However, the inherent delay originated from the DCT adder will cause instability to the modulator. A simple and power-efficient technique is proposed to absorb the delay from the DCT adder and the instability issue is therefore solved. Another proposed low-power design technique is to feed differentiated inverted quantization noise to the input of the last integrator. The modulator noise-shaping order with this proposed technique is effectively increased from two to three without adding additional active elements.

The design has been fabricated in 0.18µm CMOS technology. Measurement results showed an extremely high SNDR of over 99dB over 20kHz bandwidth, resulting in a very low figure-of-merit (FoM) in its application category.

Finally, two new circuit design ideas, low-power parasitic-insensitive switched-capacitor integrator for delta-sigma ADCs and switched-resistor tuning technique for highly linear Gm-C filter design, are presented.

Major Advisor: Gabor Temes
Committee: Pavan Hanumolu
Committee: Huaping Liu
Committee: John Conley, Jr.
GCR: Kagan Tumer


Kelley Engineering Center (campus map)
1007
Shannon Thompson
1 541 737 7234
shannon.thompson at oregonstate.edu
Sch Elect Engr/Comp Sci
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