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Event Details

MS Final Examination – Seok Min Jung

Tuesday, June 5, 2012 12:00 PM - 2:00 PM

Design of a low jitter digital PLL with low input frequency
Complex digital circuits such as microprocessors typically require support circuitry that has traditionally been realized using analog or mixed-signal macros. PLL circuits are used in many integrated applications such as frequency synthesizers and inter-chip communication interfaces. As process technologies advance and grow in complexity, the challenge of maintaining required analog elements and performance for use in circuits such as PLLs grows. Recently, digital PLL (DPLL) has emerged as an alternative to analog PLL to overcome many constraints such as low supply voltage, poor analog transistor behavior, larger area due to integrated capacitor and process variability. However, DPLLs have high deterministic jitter due to quantization noise of time-to-digital converter (TDC) and digitally-controlled oscillator (DCO) and struggle with random jitter of oscillator. In this thesis, hybrid analog/digital proportional/integral control is used to suppress TDC quantization error and digital phase accumulation techniques to mitigate DCO quantization error. VCO phase noise was reduced using an embedded voltage-mode feedback. This feedback loop is implemented by using a switched-C circuit which converts frequency to current. Designed in a 130nm CMOS process, the proposed DPLL generates more than 1GHz output frequency with low input frequency and achieves superior jitter performance compared to conventional DPLL in simulations.

Major Advisor: Pavan Hanumolu
Committee: Gabor Temes
Committee: Huaping Liu
GCR: Thomas Schmidt

Kelley Engineering Center (campus map)
Shannon Thompson
1 541 737 7234
shannon.thompson at oregonstate.edu
Sch Elect Engr/Comp Sci
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