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PhD Final Oral Examination – Amr Elshazly


Monday, June 18, 2012 2:00 PM - 4:00 PM

Performance Enhancement Techniques for Low Power Digital Phase Locked Loops
Recent developments in the integrated circuit fabrication technology coupled with circuit and system design techniques have paved the way for implementing high performance digital systems. This trend is driven by the performance of digital systems. However, the performance of analog circuits do not necessarily improve. As a result, it has become a necessity to employ highly digital integrated circuits in order to realize high performance with minimal power and area.

In this thesis, both circuit and system enhancement techniques to improve performance of clock generators are discussed. A digital PLL that employs an adaptive and highly efficient way to cancel the effect of supply noise on PLL jitter based on a background digital calibration; a supply regulated DPLL that uses low power regulator to achieve low jitter and high supply noise rejection; a digital multiplying DLL (MDLL) that obviates the need for high-resolution TDC and achieves sub-picoseconds jitter and excellent supply noise immunity; and a high resolution TDC based on a switched ring oscillator are presented. Measured results obtained from the prototype chips are presented to illustrate the proposed design techniques.

Major Advisor: Pavan Hanumolu
Committee: Gabor Temes
Committee: Karti Mayaram
Committee: Un-Ku Moon
GCR: Abi Farsoni


Kelley Engineering Center (campus map)
1007
Shannon Thompson
1 541 737 7234
shannon.thompson at oregonstate.edu
Sch Elect Engr/Comp Sci
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