Oregon State University

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PhD Oral Preliminary Examination – Jacob Postman


Wednesday, November 28, 2012 12:00 PM - 2:00 PM

On-Chip Interconnect Circuits in Digital CMOS Designs

For the past half century, CMOS process scaling has followed Moore's law, approximately doubling transistor density every 18 months. While locally routed wires have generally scaled with transistor size, longer wires have scaled at a slower rate and in some cases have grown larger as chip size and complexity have increased. Wires routed for non-local communication now consume a large and increasing portion of the power, thermal and area budgets in CMOS designs.

The goal of this research is to investigate methods of reducing the energy required for on-chip communication, primarily through the use of low-voltage swing signaling.

A network-on-chip routing architecture will be presented that uses complementary architectural and low-voltage swing signaling techniques to significantly improve the latency, throughput and power of an on-chip network. Next, on-chip signaling circuits will be presented that improve the suitability of low-voltage swing signaling for short wire lengths and reduced supply voltages. Finally, early results will be presented on a proposed system for improving the energy efficiency of an arbitrary digital CMOS design through the automated insertion of low-voltage swing signaling circuits.

Major Advisor: Patrick Chiang
Committee: Karti Mayaram
Committee: Ben Lee
Committee: Pavan Hanumolu
GCR: Joseph Zaworski 


Kelley Engineering Center (campus map)
3057
Nicole Thompson
1 541 737 5556
Nicole.Thompson at oregonstate.edu
Sch Elect Engr/Comp Sci
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