Oregon State University

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Event Details

PhD Final Oral Examination – Jon Guerber

Tuesday, December 4, 2012 10:00 AM - 12:00 PM

Efficient SAR ADC Design though Time and Statistical Information Utilization
Analog to digital converters are the interface between the analog natural environment and the digital word of computing. In an industrial and consumer electronic marketplace that is increasingly demanding greater real-world interactivity in portable and distributed devices, analog to digital converter efficiency and performance are being carefully examined. One architecture, the successive approximation (SAR) analog to digital converter (ADC), has become popular for its high energy efficiency at mid-speed and resolution requirements owing to its one core single bit quantizer, lack of residue amplification, and large digital domain processing allowing for easy process scaling.

This work examines the traditional binary capacitive SAR ADC time and statistical information and proposes new CMOS structures that optimize ADC performance. The Ternary SAR (TSAR) uses quantizer delay information to enhance accuracy, speed and power consumption of the overall SAR while providing multi-level redundancy. The early reset merged capacitor switching SAR (EMCS) identifies lost information in the SAR subtraction and optimizes a full binary quanitzer structure for a three-level MCS DAC. Residue shaping is demonstrated in SAR and pipeline configurations to allow for an extra bit of signal to noise quantization ratio (SQNR) due to multi-level redundancy.

Finally, the feedback initialized ternary SAR (FITSAR) is proposed which splits a TSAR into separate binary and ternary sub-ADC structures for speed and power benefits with an inter-stage encoding that not only maintains residue shaping across the overall SAR, but allows for a nearly optimally minimal energy consumption for capacitive ternary DACs. Overall, the incorporation of time and statistical information into the typical successive approximation IC design will be shown to push the bounds of efficiency that have been previously accepted for general purpose analog to digital converters.

Major Advisor: Un-Ku Moon
Committee: Pavan Hanumolu
Committee: Gabor Temes
Committee: Huaping Liu
GCR: Brady Gibbons

Kelley Engineering Center (campus map)
Nicole Thompson
1 541 737 3617
Nicole.Thompson at oregonstate.edu
Sch Elect Engr/Comp Sci
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