Energy and Area Efficient Analog-to-Digital Architectures and Circuit Techniques
Data converters are ubiquitous building blocks of a signal chain. The rapid increase in communication and connectivity devices presents new avenues for pushing the state of the art in analog to
digital converters (ADC). Techniques for improving resolution, bandwidth, linearity and bit-error rate, while reducing the power, energy and area is the motivation for this research. This research
focuses on achieving this goal by enabling power, energy and area efficient ADC techniques.
The following techniques are proposed for enabling power, area and energy efficient analog to digital converter techniques.
A capacitor switching scheme for successive approximation ADC is introduced to enable 93.4% energy reduction and 75 % reduction in capacitor area as compared to a conventional SAR ADCs.
Asynchronous correlated level shifting technique for improving current source linearity and power supply rejection ratio of zero crossing based circuits is proposed. This technique enables
asynchronous ADC architectures for energy efficient system.
Class-A+ and Replicated Parallel Gain Enhancement (RPGe) amplifiers are introduced as parallel gain enhancement techniques for switched capacitor circuits. A prototype pipelined ADC using RPGe
amplifier achieves 74.7 dB SNDR, 90.8 dB SFDR, 87 dB THD at 20 MS/s. Built in 1P4M 0.18 um technology and operating at 1.4 V supply, the ADC consumes 6.77 mW. The ADC occupies 3.06 sq.mm and has a
figure of merit of 75 fJ /conversion step.
A digital correction technique for detecting and correcting bit-error rate in ADCs is proposed. This multi-path ADC technique squares the bit-error rate of the ADC without consuming additional
analog power. The area increase is negligible compared to the conventional modular redundancy techniques. This technique can be applied to digitally detect and correct single event transients
occurring in ADCs. A three-path ADC can restore the ADC performance independent of the input signal frequency and number of errors in a given single path.
Major Advisor: Un-Ku Moon
Committee: Pavan Hanumolu
Committee: Gabor Temes
Committee: Raviv Raich
GCR: Abi Farsoni