Oregon State University

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PhD Oral Preliminary Examination – Eric Donkoh


Thursday, April 4, 2013 3:00 PM - 5:00 PM

Design and Modeling of Low Power Register Files
Register Files (RFs) are ubiquitous in modern microprocessor design, contributing approximately 30% of 32nm IA core power. The goal of the research is two-fold. First, it will explore low power design techniques to reduce RF leakage and dynamic power at minimum delay and area cost. We will analyze power distribution in modern microprocessor and propose effective ways to reduce power in critical power blocks like the read/write bitline and decoders of an RF. An essential component of low power design is an accurate power, area, and timing prediction for early architectural and design space tradeoff analysis. Existing power models are particularly unsuited for custom RF which constitutes over 75% of RF on high performance processors. These models typically assume a generic SRAM topology and are not adaptable to unique topologies of custom RFs. Furthermore, these models do not accurately address design optimizations such as device sizing, data gating, segmentation, and device stacking that significantly impacts the power profile of an RF. The second part of this research will develop a new power, area, delay models that address these key limitations. A customizable power, area, and delay model that is adaptable to different RF topologies and array structure such as SRAM, and ROM will be developed. The modeling approach will be a hybrid of empirical reference data and analytical equations.

Major Advisor: Patrick Chiang
Committee: Shih-Lien Lu
Committee: Bibiche Geuskens
Committee: Arun Natarajan
GCR: Abi Farsoni 


Kelley Engineering Center (campus map)
4107
Nicole Thompson
1 541 737 7234
Nicole.Thompson at oregonstate.edu
Sch Elect Engr/Comp Sci
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