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MS Final Examination – Yichen Zhao


Tuesday, May 28, 2013 10:00 AM - 12:00 PM

Design and FPGA Implementation of Digital Transmission Over Severe ISI Channels
Inter-symbol interference (ISI) is the major factor that complicates the realization of high-data-rate digital communication. Current designs face two main challenges: how to efficiently utilize the available bandwidth and how to reduce the hardware complexity of the transmitter and receiver. Traditional solutions use a single-band architecture.  When ISI is severe, it requires a decision feedback equalizer to mitigate, which usually causes a high complexity and power consumption. In this thesis, the analysis and FPGA implementation of a multi-band architecture is studied. Specifically, a four-band architecture is presented in detail, compared with the single-band approach in terms of bit-error rate (BER) and power requirements.

First, several basic theories required are provided for convenience of understanding the major development in this thesis in terms of simulation and FPGA implementation. Then the channel characteristics, like frequency and impulse responses, are analyzed for a four-band architecture. The single- and four-band architectures are introduced separately and optimized in detail. Simulation results of both architectures are verified through FPGA implementation in the Xilinx Virtex-5 development board. Finally, BERs of the two architectures are compared from both simulation and FPGA implementation results.

Major Advisor: Huaping Liu
Committee: Alan Wang
Committee: Bechir Hamdaoui
GCR: Chinweiki Eseonu


Kelley Engineering Center (campus map)
1007
Nicole Thompson
1 541 737 3617
Nicole.Thompson at oregonstate.edu
Sch Elect Engr/Comp Sci
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