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PhD Oral Preliminary Examination – Vikas Shilimkar


Wednesday, May 29, 2013 8:00 AM - 10:00 AM

Enabling Metal-Fill-Aware Design of Integrated Circuits
In advanced integrated circuit (IC) processes, the metal fill inserted to meet density requirements degrades the interconnect and passive component performance and ultimately overall circuit performance. Accounting for this degradation through electromagnetic and equivalent circuit modeling is a critical aspect of IC design. However, electromagnetic simulation of interconnects and passive components including metal fill quickly becomes prohibitive due to the large problem size. The modeling methods in the literature are limited in accuracy and ignore important effects.

The goal of this research is to investigate fast and scalable modeling methods for interconnects and passive components in the presence of metal fill. A novel three dimensional problem reduction approach to model capacitance of metal fill in multi-conductor interconnects is proposed. Further, a custom electromagnetic solver technique for modeling metal fill in passive components is proposed. For the model verification, a systematic measurement characterization approach is being developed. Ultimately, this research will enable efficient metal-fill-aware design of integrated circuits through fast and accurate models for interconnects and passive components in the presence of metal fill.

Major Advisor: Andreas Weisshaar
Committee: Karti Mayaram
Committee: Patrick Chiang
Committee: Albrecht Jander
GCR: Wade Marcum


Kelley Engineering Center (campus map)
3114
Nicole Thompson
1 541 737 3617
Nicole.Thompson at oregonstate.edu
Sch Elect Engr/Comp Sci
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