Oregon State University

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Event Details

PhD Final Oral Examination – Tao Jiang

Monday, June 10, 2013 1:00 PM - 3:00 PM

Design Techniques for Ultra-High-Speed, Medium-Resolution, Low-Power Analog-to-Digital Converters
Ultra-high-speed (>10 GS/s), medium-resolution (5~6 bit), low-power (<50 mW) analog-to-digital converter can find it application in the areas of digital oscilloscopes and next-generation serial link receivers. There are several challenges to enable a successful design, however. First, time-interleaved architecture has to be employed in order to achieve over 10 GS/s sampling rate, with the trade-off of the number of channels and the sampling rate in each channel. Phase misalignment and channel mismatch must be considered too. Second, timing accuracy, especially dynamic jitter of sampling clock becomes a major concern at ultra-high frequency, and certain techniques must be taken to address it. Finally, to achieve low power consumption, Flash architecture is not suitable to serve as the sub-ADC, and a low-power sub-ADC that can work at relatively high speed need to be designed.

A single channel, asynchronous successive approximation (SA) ADC with improved feedback delay has been fabricated in 40nm CMOS. Compared with a conventional SA structure that employs a single quantizer controlled by a digital feedback logic loop, the proposed SA-ADC employs multiple quantizers for each conversion bit, clocked by an asynchronous ripple clock that is generated after each quantization. Hence, the sampling rate of the 6-bit ADC is limited only by the six delays of the Capacitive-DAC settling and each comparator’s quantization delay, as the digital logic delay is eliminated. Measurement results of the 40nm-CMOS SA-ADC achieves peak SNDR of 32.9dB at 1GS/s and 30.5dB at 1.25GS/s, consuming 5.28mW and 6.08mW respectively, leading to FoM of 148fJ/conversion-step and 178fJ/conversion-step, in a core area less than 170µm by 85µm.

Cascading three 2-bit Flashes in a row, a 2-bit/step asynchronous SA ADC with improved feedback loop is designed to achieve even higher sampling rate. Simulated in 28nm CMOS under 0.9V power supply, the proposed 1.5GS/s 6bit 2-bit/step asynchronous SA ADC with improved feedback loop can complete the conversion within 640ps, while consuming 2.7mW under typical condition. FFT results show that it can achieve 37dB SNDR at Nyquist input frequency of 750MHz.

Based on the previous work of sub-ADC, a 12-GS/s 5-b 50-mW ADC is designed in 40nm CMOS with 8 time-interleaved channels of Flash-SA hybrid structure each running at 1.5 GS/s. A modified bootstrapped switch is used in the track-and-hold circuit, introducing a global clock signal to synchronize the sampling instants of each individual channel, therefore improve the phase alignment and reduce distortion. The global clock is provided by a CML buffer which is injected by off-chip low-noise sine-wave signal, so that the RMS dynamic jitter is low for better ENOB performance. Measurement results show that the 12GS/s ADC can achieve a SNDR of 26.5dB with the input signal frequency around DC and 22.4dB around 4GHz, consuming 32.1mW, leading to FoM of 155fJ/conversion-step, in a core area less than 800µm by 500µm.

Major Advisor: Patrick Chiang
Committee: Gabor Temes
Committee: Huaping Liu
Committee: Albrecht Jander
GCR: Abi Farsoni

Kelley Engineering Center (campus map)
Nicole Thompson
1 541 737 3617
Nicole.Thompson at oregonstate.edu
Sch Elect Engr/Comp Sci
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