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PhD Final Oral Examination – Jacob Postman


Tuesday, June 11, 2013 2:30 PM - 4:30 PM

Energy Efficient Communication Across On-Chip Wires in Digital CMOS
For the past half century, CMOS process scaling has followed Moore’s law, approximately doubling transistor density every 18 months. While locally routed wires have generally scaled with transistor size, longer wires have scaled at a slower rate and in some cases have grown larger as chip size and complexity have increased. Wires routed for non-local communication now consume a large and increasing portion of the power, thermal and area budgets in CMOS designs. Additionally, dynamic energy expended in driving locally routed wires has become comparable to that expended in logic.

The goal of this research is to investigate methods of reducing the energy required for on-chip communication, primarily through the use of low-voltage swing signaling.

A network-on-chip routing architecture will be presented that uses complementary architectural and low-voltage swing signaling techniques to significantly improve the latency, throughput and power of an on-chip network. On-chip signaling circuits will then presented that improve the suitability of low-voltage swing signaling for short wire lengths and reduced supply voltages. Finally, a system for improving the energy efficiency of wire loads in digital CMOS through the automated insertion of low-voltage swing signaling circuits will be presented.

Major Advisor: Patrick Chiang
Committee: Karti Mayaram
Committee: Huaping Liu
Committee: Bechir Hamdaoui
GCR: Joseph Zaworski


Kelley Engineering Center (campus map)
1007
Nicole Thompson
1 541 737 3617
Nicole.Thompson at oregonstate.edu
Sch Elect Engr/Comp Sci
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