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PhD Oral Preliminary Examination – Wei Li


Thursday, June 20, 2013 2:00 PM - 4:00 PM

Low-Power 12-bit SAR ADC with Digital Foreground Calibration
IC designers are currently facing the challenges of reduced CMOS physical feature size and supply voltage scaling. Hence, ADCs which can deliver satisfactory resolution while utilizing state-of-art fabrication processes to save power are in high demand. This thesis is focused on a low-power 12-bit 12.5-MHz bandwidth medium-resolution successive approximation (SAR) ADC with these properties.

The thesis includes two innovative methods. To reduce power dissipation, a power saving operation strategy has been proposed. Also, several foreground calibration methods for SAR ADCs have been found which can also reduce power dissipation. The schematic-level simulation predicts a Figure-of-Merit (FoM) of 28fJ/conv., which is among the best of ADCs of similar resolution.

Major Advisor: Gabor Temes
Committee: Terri Fiez
Committee: Thinh Nguyen
Committee: Alan Wang
GCR: Margaret Niess 


Kelley Engineering Center (campus map)
3114
Nicole Thompson
1 541 737 3617
Nicole.Thompson at oregonstate.edu
Sch Elect Engr/Comp Sci
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