Oregon State University

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PhD Oral Preliminary Examination – Samira Zali Asl


Monday, September 23, 2013 3:00 PM - 5:00 PM

Architectural Solutions for Analog Imperfections in ΔΣ Analog-to-Digital Based Systems
For today’s ubiquitous portable devices, innovative integrated circuits with high performance yet very low power are necessary. As these devices are used to communicate and sense signals in the environment, analog-to-digital converters and systems represent one of the most challenging aspects in the overall design. Fundamentally, this is due to the inherent imperfections in integrated circuit process technology. In this thesis, noise shaping techniques are used to mitigate analog inaccuracies such as non-linearity and mismatch. These approaches are applied to ΔΣ Analog-to-Digital based systems.

Two systems are presented in this work. The first is an architectural technique to highlight the benefits of low power, highly digital VCO-based analog-to-digital converters (ADCs). It overcomes the limited SFDR due to VCO non-linearity. In this approach, a multi-loop delta-sigma (ΔΣ) ADC architecture is introduced that has a multi-rated VCO-based ADC in its second stage. A custom IC prototype of this architecture fabricated in a 130nm 1P8M CMOS process achieves 77.3dB signal-to-noise-ratio (SNR) over a 4 MHz signal bandwidth with a power consumption of 13.8mW.

The second system includes a new dynamic element matching (DEM) algorithm in the reference generating circuit of a ΔΣ modulator. Conventional DEM increases in-band noise due to intermodulation between the DEM tone and quantization error. In the proposed technique, by completing an integer multiple of the DEM cycles within one ΣΔ cycle, the DEM tone is moved to an integer multiple of the ΣΔ sample rate. As a result, with no additional circuitry or power consumption, the new DEM technique prevents any increase in the in-band noise. To prove its effectiveness, the DEM algorithm is embedded in a temperature-to-digital Converter (TDC) which requires a high precision reference. This TDC consists of a BJT-based temperature sensor followed by a 2nd-order feed-forward ΔΣ ADC as a readout circuit. It is fabricated in an 180nm 1P5M CMOS process consuming 5uA current from 1.4V VDD achieving resolution of 25mK/Conversion.

Major Advisor: Terri Fiez
Committee: Karti Mayaram, Gabor Temes, Arun Natarajan
GCR: Wade Marcum


Kelley Engineering Center (campus map)
1005
Nicole Thompson
1 541 737 7234
Nicole.Thompson at oregonstate.edu
Sch Elect Engr/Comp Sci
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