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Event Details

PhD Oral Preliminary Examination – Joseph Crop

Friday, December 6, 2013 4:45 PM - 6:45 PM

Methods to Improve the Reliability and Resiliency of Near/Sub-Threshold Digital Circuits
Energy consumption is one of the primary bottlenecks to both large and small scale modern compute platforms. Reducing the operating voltage of digital circuits to voltages where the supply voltage is near or below the threshold of the transistors has recently gained attention as a method to reduce the energy required for computations by as much as 6X. However, when operating at near/sub-threshold voltages, imperfections in transistor manufacturing, changes in temperature, and other difficult to control factors cause wide variations in the timing of CMOS circuits due to an increased sensitivity at lower voltages. These increased variations result in poor aggregate performance and cause increased rates of error occurrence in computation.

This work introduces a design automation technique that is used to aid in low-voltage digital standard cell synthesis. Two circuit-level techniques are also introduced that aim to improve the reliability and resiliency of digital circuits by means of completion/error detection. These techniques are shown to improve speed and lower energy consumption at low overheads compared to previous methods. Most importantly, these circuit-level methods are specifically designed to operate at low voltages and can themselves tolerate variations and operation in harsh environments.

Major Advisor: Patrick Chiang
Committee: Gabor Temes
Committee: Karti Mayaram
Committee: Ben Lee
GCR: Byron Marshall 

Kelley Engineering Center (campus map)
Nicole Thompson
1 541 737 3617
Nicole.Thompson at oregonstate.edu
Sch Elect Engr/Comp Sci
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