Oregon State University

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Event Details

PhD Final Oral Examination – Vikas Shilimkar

Friday, January 3, 2014 3:00 PM - 5:00 PM

Enabling Metal-Fill-Aware Design of Integrated Circuits
In advanced integrated circuit (IC) processes, the metal fill inserted to meet foundry imposed density requirements degrades the performance of interconnects and passive components which ultimately affects the overall circuit performance. Accounting for this degradation through electromagnetic and equivalent circuit modeling is becoming a critical aspect of IC design. However, electromagnetic simulation of interconnects and passive components including metal fill quickly becomes prohibitive due to the large problem complexity while the modeling methods in the literature are limited in accuracy  and ignore important effects.

This thesis investigates fast and scalable modeling methods for interconnects and spiral inductors in the presence of metal fill. A novel three dimensional problem reduction approach is proposed to model the parasitic capacitance due to metal fill in multi-conductor interconnects. Further, a unique technique for modeling metal fill in spiral inductors is proposed. A systematic on-wafer measurement characterization approach is developed for model verification.

Ultimately, the research presented in this thesis will enable efficient metal-fill-aware design of integrated circuits through fast and accurate models for interconnects and passive components in the presence of metal fill.

Major Advisor: Andreas Weisshaar
Committee: Karti Mayaram
Committee: Patrick Chiang
Committee: Alan Wang
GCR: Wade Marcum 

Kelley Engineering Center (campus map)
Nicole Thompson
1 541 737 3617
Nicole.Thompson at oregonstate.edu
Sch Elect Engr/Comp Sci
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