Oregon State University

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Event Details

PhD Oral Preliminary Examination – Allen Waters

Tuesday, January 21, 2014 9:00 AM - 11:00 AM

Synthesizable Analog-to-Digital Converter Design
CMOS technologies continue to scale devices to smaller sizes, allowing for faster operation and reduced power consumption. This trend is expected to continue and designs will be ported to these new processes to take advantage of the reduced power, delay and area. Digital circuits scale easily; since the design layouts are automatically synthesized from Verilog descriptions, there is little design cost to port to a new process. Unfortunately, analog circuits are manually laid out, so process scaling is difficult and time-consuming.

This work discusses creating custom cells that provide basic analog functionality, and adding these alongside the standard digital cell library. With the added custom cells, analog circuits may be described in Verilog code and automatically laid out. Two different synthesized ADC structures are presented, each implemented in both 130nm and 65nm CMOS to illustrate the ease of process scaling.

Major Advisor: Un-Ku Moon
Committee: Karti Mayaram
Committee: Gabor Temes
Committee: Huaping Liu
GCR: Karen Shell 

Kelley Engineering Center (campus map)
Nicole Thompson
1 541 737 3617
Nicole.Thompson at oregonstate.edu
Sch Elect Engr/Comp Sci
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