Oregon State University

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PhD Oral Preliminary Examination – Yue Hu


Wednesday, March 26, 2014 3:00 PM - 5:00 PM

Design Techniques for Analog-to-Digital Data Converters using Time Information
Time-domain data conversion (TDC) has recently drawn increased research attention for its highly digital nature in favor of process technology scaling, furthermore, as the time information carried by binary voltage is much less sensitive to voltage noise compared to conventional voltage domain operation. However, the challenge lies in the methodology of merging voltage and time domain operation while maintaining the overall data conversion accuracy and power efficiency. This work has a focus on investigation of novel data conversion topology based on classic voltage domain operation that is capable of generating time information, which brings in improvement to analog-to-digital converter (ADC) resolution and system stability without power penalty.

In the first approach, a novel continuous-time (CT) delta-sigma modulator (DSM) using a time-interleaved quantizer is proposed and implemented. Along with the doubled sample rate, the proposed architecture utilizes time information to perform correlated coupling between the two quantizer channels. The measurement results achieves 2nd order noise coupling from the interleaved quantizer itself without extra phases. More importantly, excess loop delay of two full sample clocks is compensated by time-domain signal coupling; the resulted CT DSM is fully stabilized in 120MHz sampling rate.

In the second approach, a new category of pulse-width-modulation (PWM) scheme is proposed and described. An ADC structure is further proposed utilizing this novel voltage-to-time portal followed by a first order noise-shaped switched-ring-oscillator TDC quantizer. This ADC topology takes advantage of the TDC speed scaling for its digitized operation to boost the overall ADC resolution and signal bandwidth, while the voltage to time front-end is able to remain at a much lower speed than the TDC thanks to the proposed technique. This is the first work that decouples the PWM modulation rate from ADC sampling speed without distortion penalty.

Major Advisor: Un-Ku Moon
Committee: Arun Natarajan
Committee: Huaping Liu
Committee: Patrick Chiang
GCR: Maggie Niess 


Kelley Engineering Center (campus map)
1007
Nicole Thompson
1 541 737 3617
Nicole.Thompson at oregonstate.edu
Sch Elect Engr/Comp Sci
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